Enterprise-Class NAND: Coming to a Server Near You
Hey guys. The MAST folks asked me to get the blog up to speed on a very exciting announcement—our Enterprise NAND. In a nutshell, Enterprise NAND is a very high endurance SLC NAND device. It has a write/erase cycle endurance of 1 million cycles. Seriously cool–that’s 10X standard NAND. So, what does it mean? Well, it means that NAND, in its various flavors, can play and perform in everything from thumb drives to performance SSDs and now, it also has a home in high endurance, high-transaction applications like data servers. And with the kinds of endorsements it’s getting from the likes of Sun Microsystems and Violin memory, I think we’re seeing NAND really come into its own. Anyway, check out the short video and the announcement for more info.
httpv://www.youtube.com/watch?v=lQAxNV3b6Ec
14 Comments to “Enterprise-Class NAND: Coming to a Server Near You”
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Kevin, is there any write performance penalty in order to extend erase cycle in enterprise NAND technology, comparing to typical NAND?
Hi Nelson. Yes, there is a write-performance penalty for extended-cycling NAND. This penalty varies by product and process technology, so I can’t provide an actual number. But–keep in mind that the applications that will take advantage of this technology will be less sensitive to write performance, because they either write in the background (which doesn’t impact system performance), or they have very large arrays that essentially spreads the write delay out among multiple NAND channels (parallelism).
Kevin,
is this a monolithic 32Gb SLC die? That’s impressive! Which technology node (I assume 34nm)? And finally, is this a “standard” NAND configured and/or tested to achieve 1M cycles or there were some design improvements to achieve this?
Regards,
Luca
Hey Luca. No, actually it’s an 8Gb die in a QDP. Regarding the standard/configured question–Micron has the ability to “tune” our products based on the performance/endurance requirements of different applications. In this case, our goal was to provide enterprise-class reliability to applications where endurance was the first design priority.
Hi Kevin – How does this compare to Fusion-IO?
Hey Eddie–I am not completely familiar with Fusion IO’s technology so I can’t really make a fair comparison, but I think the fundamental difference is their expertise resides in their controller technology while Enterprise NAND allows standard NAND controllers to take advantage of the extended cycling.
Hi Kevin,
Is 100K SLC chip version the same as 1M version?
If the same, does this mean that there is some additional internal to the chip processing to prevent bit flip accumulation, or “special” wear leveling inside the chip? Or different “rules” are used to write the data?
If I have a really good flash controller (in terms of ECC/wear leveling), will I see 10x improved write endurance?
Kevin,
Will one benefit from this new flash, when a very good flash controller, in terms of ECC/wear leveling algorithms is used?
Are there any changes to the chip itself?
Thanks
Hi Wesley, Yes–this is the same die as Micron’s 100K SLC (50nm 8Gb). We have been able to extend the write endurance through proprietary methods and guarantee the same failure rates. By itself the ECC or wear leveling of the flash controller cannot improve the physical endurance capability of the flash technology, but it can improve the effective reliability that the customer will experience.
Hi Kevin, thanks for your response.
To make sure that I understand – and simplifying – Let’s assume that my storage is just one chip and I’m continuously writing to the same LBA. With your new approach the write endurance will be improved to 1M program cycles. How will write endurance improve further, if at all, if I use an external controller with wear leveling/ECC?
Hey Wesley–great questions.
The endurance specification is on a per-block basis. Therefore, you are correct that if you wrote continuously to the same block, the endurance is 1M cycles for that block (assuming no logical to physical block translation). With proper wear-leveling algorithms, the write cycles are spread out among the different physical blocks within the NAND array, so the maximum number of program cycles is effectively 1M times the number of blocks in the NAND array if you are only writing one block worth of data at a time.
To properly determine NAND endurance in terms of time, you need to know the total amount of data written per day and the total NAND system density. Let’s use the example of a single 8Gb (1GB) NAND flash with 1GB of data written per day. Without wear leveling the endurance using 1M cycle NAND would be approximately 244 days if we wrote to the same block each time (the block size is 256KB, so 1GB of data has to be written to the same block 4,096 times each day). With wear leveling, the math is much simpler since 1GB written to a 1GB array per day means 1M days of endurance, which is over 2,700 years! 1M cycle NAND would obviously be overkill for this example, but imagine enterprise applications where terabytes (1,000s of GB) are written every day, and you can begin to see how extending cycling NAND enables new applications.
ECC is not related to NAND endurance. In the data sheet of our NAND devices, we specify the ECC requirements that the flash controller must provide in order to guarantee a certain bit error rate. For example, for Micron’s 50nm MLC products we specify 8 bits of ECC. The trend has been for ECC requirements to increase as NAND manufacturers shrink their process technology. Having more ECC does enable a lower bit error rate, however there are diminishing returns, plus there are limits on the number of ECC bits based on the spare area to store the ECC data in the NAND array.
Sorry for the long-winded answer, but you have asked some very good questions and I wanted to provide a complete reply.
Hi. Your site displays incorrectly in Firefox, but content excellent! Thanks for your wise words.
Kevin,
Can you explain or point to a reference that explains why Flash cells wear out in the first place? As there are no ‘mechanics’ involved I was wondering what is causing the wear.
thanks,
Gilbert
Hi Gilbert,
The NAND technically does not wear in terms of losing the memory cell, but there are charge loss, disturb, and other effects on the cell that limit the number of program/erase cycles. There’s a great overview on http://www.nand.com/#whatis