But we see the cloud as a positive driver for storage both in servers and on devices, and we’re not the only ones. See why one software company thinks that better access to the cloud will mean that you’ll want even more high-performance storage on your mobile device—not less.

Process shrinks require tinier, more-complex cells, which translates to lower performance and endurance. This has been true for generations of NAND process shrinks and is more or less a byproduct of the laws of physics. We’re approaching atomic dimensions (a single copper atom is .25nm), and it takes some extraordinary science to design circuits that can hold electrical charges at this scale.

With this new design however, we included some innovative new technology that will allow our 20nm NAND to eventually hit the same endurance and performance specifications as our current-generation NAND (25nm). We’re also continuing our pattern of keeping ECC (error correction code) requirements a generation lower than the competition. Our 20nm NAND will have similar ECC requirements to some competitors’ current NAND products, meaning they won’t require more ECC from the controller.

These are significant advancements that helps provide a viable path for NAND scaling and development. The end result is a great new product that’s going to enable even more innovation in mobile storage applications.

It’s impossible to predict which tablet versions will catch on with consumers and which ones will quietly fade out of circulation, but we do know that NAND flash will be in high demand for this product segment.

According to the iSuppli report, shipments of NAND for tablet devices are expected to reach 1.7 billion (yes billion!) GB in 2011, which is nearly a 300 percent increase over this year’s expected 428 million GB shipped. And this rising tide isn’t expected to pull back anytime soon—the report forecasts 8.8 billion GB in NAND shipments by 2014.

I had the chance to get some additional perspective on the report from Michael Yang at iSuppli, the analyst who wrote the report, and here’s what he had to say: “The NAND market is shifting from commodity-driven to embedded-driven, led by Smartphones and the rising interest in tablets. With at least 30 models anticipated before the end of the year, tablets’ rosy outlook is a boon for NAND flash memory. We expect average density of these tablets to grow from 28GB this year to 65GB in 2014.”

From the Micron perspective, we’re excited about the end products making good use of the innovations we’ve made in NAND. With the rise in smartphone offerings, along with the increased adoption of SSDs in the enterprise, we’ve been working hard to ensure that we’re well positioned to meet the growing NAND demand. And now, with tablet computing coming on strong, the continued strides we’re making in NAND has an even greater impact in the end product designs.

Increasing storage (NAND) capacity is one area we’ve focused on. A key example of this is the milestone we reached this summer by adding three-bits-per cell of NAND storage on our 25-nanometer NAND process. This provides 8GBs of NAND storage on a single device – that’s smaller than your keyboard key – and opens up an even broader range of possibilities for flash memory design.

We’re continuing to push the envelope and we’ll be talking about new memory breakthroughs in the months to come, so stay tuned. Whether it’s for today’s emerging tablet market or tomorrow’s “next big thing,” NAND flash will be an essential ingredient in the world’s most popular gadgets.

In traditional system architectures using NAND, the host controller assumes responsibility for all NAND management functions, including block management, wear leveling, and error correction code (ECC). In these instances, the host controller has to take into account the NAND ECC requirements for potentially multiple generations (process nodes) and multiple cell technologies (1/2/3 bits per cell), as well as the requirements from multiple suppliers. Additionally, flash error management is rapidly moving beyond what today’s ECC schemes are capable of and in the near-future will require more advanced ECC and signal processing algorithms.  On the other hand, the other NAND management functions are almost solely dependent on the application, something the host controller and system manufacturers are best suited to develop. The solution? Let the NAND manufacturers worry about the flash error management.

As a founding member of the ONFI Working Group, Micron has teaming up with other NAND Flash companies to create standards to ensure our customers can take advantage of the great strides we’re making in NAND flash without having to worry about the error management requirements. One of these standards is the EZ-NAND protocol, or ECC Zero NAND. In essence, EZ-NAND alleviates the burden of the host controller to implement and keep pace with the fast changing ECC requirements that is circumstance of NAND flash process shrink. Here’s a side-by-side comparison of a traditional NAND architecture compared to the EZ-NAND architecture:

For more, check out this presentation from Pete Feeley of Micron that was given at the 2010 Flash Memory Summit. Or, drop me a question in the comments section and I’ll be in touch.

The video below features highlights from a presentation given by Intel and Micron executives at our 25nm announcement. Learn what our aggressive scaling strategy means for the future of storage and the next generations of NAND.

In fact, our 34nm process is so solid, we’ve even moved our super-high cycling Enterprise NAND parts to it. We just announced 34nm SLC and MLC Enterprise NAND parts that can hit 300,000 and 30,000 cycles, respectively. These new parts deliver unmatched density, cost-efficiency, and reliability and will open up new potential for NAND storage in enterprise applications.  Watch my quick explanation below to understand why.

Multiple Routes to Quality & Reliability
More than any other segment, enterprise apps want high quality and high reliability NAND. While we create specially-designed “Enterprise NAND” that delivers super-low defect rates and high endurance for specific applications, there are other methods to increase endurance. For instance, some of our customers take advantage of the high density of our newest NAND to build systems with a surplus of capacity. Because there’s extra density, each cell is written less often, and the effective life of all the NAND goes up dramatically. Advanced wear-leveling algorithms will also provide advanced NAND with better endurance levels than it achieved in the past.

NAND Control Will See Breakthrough Innovation
Yes, developing NAND controller technology is more challenging with each process node, but it is also an area of heavy focus and technology investment. Micron, with SSD’s and other technologies in development, is ensuring that NAND is fit for the enterprise. Controllers will continue to improve along with the NAND changes—this is an area of tremendous innovation, and mirrors what occurred in HDD evolution.

Scaling—The Path Ahead
Some have suggested that only legacy process NAND is fit for enterprise applications. That’s simply not true. As noted above, there are multiple methods to achieve enterprise-class performance on advanced process NAND. And while we will continue to provide some legacy NAND for key applications, most enterprise customers will want to take advantage of the benefits new technology presents. In fact, this week we will introduce a new portfolio of ultra-reliable Enterprise NAND products designed on our mature 34nm NAND process – enabling the high density and better cost structure that only advanced process NAND can provide. Make sure to stay tuned to our blog for more on that later this week.

And we stated this summer at the Flash Memory Summit, NAND has plenty of room for further scaling improvements. Don’t let the naysayers fool you—the years ahead are going to be an exciting period of change and accelerating NAND adoption into hundreds of new applications. I’m looking forward to it.