Steve’s passion and energy left an indelible mark on Micron, the Idaho community and the technology industry at large.

Read Steve’s Bio

Read the Press Release

HMC has been in development since 2006 and represents the combined efforts of three cross-functional teams: logic layer designers, DRAM design engineers, and our advanced packaging team. These teams were challenged to think beyond the evolutionary path of memory and focus on developing a technology that would overshoot industry expectations in terms of raw bandwidth and energy efficiency—an engineer’s dream come true!

One of the more unusual challenges we faced was how to test HMC—its performance is literally off the scale, which means there’s no existing infrastructure that would be able to measure the remarkable specs it delivers. So we designed HMC to measure itself, literally—the testing capability is built right into the chip.

Now that we’re moving from the prototype stage toward actual production of this revolutionary product, the HMC Consortium (HMCC) is leading the effort to create in industry-adoptable standard and bring HMC to market.

More information:
Read the press release about HMC’s “Best Technology of 2011” award.
Learn more about HMC technology
Find out about the HMC Consortium at hybridmemorycube.org

But we see the cloud as a positive driver for storage both in servers and on devices, and we’re not the only ones. See why one software company thinks that better access to the cloud will mean that you’ll want even more high-performance storage on your mobile device—not less.

Watch our interview with Data Design’s Director of Engineering Richard Baum to see the high-performance SSD they brought to market with our Enhanced ClearNAND™ Flash. Its built-in ECC delivered exactly what they were looking for—smaller footprint, lower power consumption, and 70% less controller complexity.

Or, read the case study.

The idea behind 3DS is to use specially designed and manufactured master-and-slave DRAM die, with only the master die interfacing with the external memory controller. 3DS technology uses optimized DRAM die, single DLL per stack, reduced active logic, single shared external I/O, improved timing, and reduced load to the external world. This combination of features can improve timing, bus speeds, and signal integrity while lowering both power consumption and system overhead for next-generation modules.

In our video demo below, we show a timing limitation when reading from one rank and then from another. Due to the system limitation, there is a one-cycle gap on the data bus, which impacts overall system bandwidth.

Micron’s 3DS devices offer the opportunity to eliminate this timing gap between read accesses from one rank to another. Our 3DS device can accept READ commands to different ranks so that the data bus is in constant use.

In the second case, we are observing how data is continuous when the system issues consecutive READ commands on the same rank. A 3DS-optimized system will similarly take advantage of this tighter timing and be able to see improved data bus utilization and bandwidth when reading from different banks.

Thanks for watching, and feel free to post any questions you have for us about this emerging DRAM architecture.

To put it in perspective, a terabit (128GB) is a HUGE amount of data—according to Tech Target, it’s more than enough to store all the contents of an entire library floor of academic journals (100GB)—reams of information all packed within a single NAND package.

But you’re probably not storing thousands of academic journals. For you and me it means more storage for downloaded movies, music, e-books, and photos. You probably don’t know how many NAND die are in your phone or SSD, but you do know how much it cost, which is what process improvements like these provide—more cost-effective, better storage solutions. Intel and Micron continue to lead the industry in moving innovative new NAND solutions to production.

Let me know what you think of our latest 20nm NAND by posting a comment below, or read more about our technology leadership on our Process Innovations page.

In a Micron interview, Steve shares his thoughts about receiving the Robert N. Noyce Award, and SIA president Biran Toohey talks about Steve’s commitment and contributions to the industry. Read more about the award and watch the interview.

Dallas, Texas-based SoftLayer Technologies—the world’s largest privately owned hosting company—needed a scalable, reliable storage solution that they could count on across applications, whether they were running data sets or speeding up OS response times. So they ran a lot of tough stress tests with SSDs from multiple vendors, and at the end, our P300 stood out as the steady performer.

Watch our interview with SoftLayer’s VP of Information Systems Jacob Linscott to learn more about how our enterprise-class Real SSD™ P300 nailed their performance curve, and where he thinks SSDs are headed for the future. Or read the Case Study.

I sat down with Scott Graham, Micron’s General Manager for DRAM Solutions, to discuss HMC, its future, and Micron’s role in this groundbreaking consortium. Check out this video to find out more about the consortium and what the future holds for this revolutionary technology.

“It’s estimated that 40 exabytes of unique new information will be generated worldwide this year,” said Eby. “That’s more than in the previous 5,000 years … combined!”

Eby broke down trends affecting memory growth into three main categories…the three Cs: consume, connect and capture.

* Consume: Eby used examples of tablets, automotive infotainment, and televisions to illustrate how more and more data is being consumed.

* Connect: Eby characterized the internet of things as the next wave of connected devices ranging from household appliances to smart meters, all needing more memory. Eby also said that cloud computing will compliment, not compete with memory growth in devices and the data center.

* Capture: For this trend, Eby showed what he calls the “ultimate capture app,” using the example of a gigapan image taken by David Bergman at President Obama’s inauguration. It’s comprised of 220 images and the final image size is 59,783 X 24,658 pixels or 1.47 gigapixels. See it here