Comments for Micron Innovations Blog

Comment on Steve Appleton 1960-2012 by detroitmom

detroitmom — Sat, 04 Feb 2012 00:16:13 +0000

I am truly saddened and offer my deepest condolences to Mr Appleton’s family, friends and co workers.

Comment on Steve Appleton 1960-2012 by R.S. Melroy

R.S. Melroy — Fri, 03 Feb 2012 23:37:38 +0000

My thoughts and prayers are with him and his family.

Comment on Steve Appleton 1960-2012 by Richard M Sottosanti

Richard M Sottosanti — Fri, 03 Feb 2012 23:30:03 +0000

We are deeply saddened to hear of Steve’s passing. We came to know him while racing the Baja 1000 with Wide Open Baja. He touched our family with his frienship and generosity. We will greatly miss him.

With deepest sympathy,
Richard, Deborah, Richie, Amanda Sottosanti
RMS OFF ROAD INC.
Long Island, NY

Comment on Crucial Launches RealSSD™ C300 Drives by Richard

Richard — Wed, 01 Feb 2012 14:47:03 +0000

The issue of unpowered retention does arise in certain situations. I have a (wealthy) client who wants a computer for their summer cottage. It will be powered off for many months each winter.

Likewise, disaster-recovery spares might be preloaded with software and then put on the shelf for use when needed, interrupted only be testing every 6-12 months.

Comment on 3DS DRAM Memory Technology for Next-Generation Modules by Dr. Aftab Farooqi

Dr. Aftab Farooqi — Wed, 28 Dec 2011 20:04:29 +0000

Thanks for the comment, GullLars. Answers to your questions are noted below:

Will this technology be ready for DDR4?

Micron’s 3DS is enabled for DDR3. Please refer to the JEDEC DDR4 specifications.

And will it require specialized memory controllers, or will it work with standard memory controllers of the generation/type it is introduced?

Micron’s 3DS devices are designed to work with many existing memory controllers. The system can benefit from enhanced performance enabled by a controller which takes advantage of the seamless rank to rank timing of the 3DS devices.

I’m looking forward to this, as i hope it will provide lower cost high density RAM.

Also, will this technology make it possible to implement ECC directly in the DIMMs or ranks without MC interaction? As RAM densities increase, the BER compared to capacity and data moved becomes significant, and ECC memory becomes important for data integrity.

No. Micron’s 3DS devices don’t change any aspect of ECC. Existing memory controllers with ECC features will work well with 3DS devices.

Comment on 3DS DRAM Memory Technology for Next-Generation Modules by GullLars

GullLars — Mon, 19 Dec 2011 14:21:55 +0000

Hi,

Will this technology be ready for DDR4? And will it require specialized memory controllers, or will it work with standard memory controllers of the generation/type it is introduced?

I’m looking forward to this, as i hope it will provide lower cost high density RAM.

Comment on A Trillion Bits on a Fingertip by GullLars

GullLars — Mon, 19 Dec 2011 14:03:14 +0000

So these chips are rated for up to 333 MT/s and have an 8-bit bus = 333 MB/s. This is above ONFI 2.x and within ONFI 3.0 interface bandwidth as far as i can tell.

Moving past interface bandwidth, can a single die push 333 MB/s of read bandwidth? If so at what transfer size? And what is the maximum write bandwidth (pre-erased writes) and erase speed?

I’m curious if the R:W latency ratio has shifted further towards R than larger gemoetries.

Related to the internal speed, can you comment on page size and erase-block size? This is relevant for use in SSDs. I own a few C300 i RAID, and plan on skipping the M4 improvement before maybe going for the next generation SSD from Micron, if you provide as good a product as i suspect you will

GullLars

Comment on PCM Real-World Demo by tolerance

tolerance — Wed, 14 Dec 2011 17:07:19 +0000

Thanks for the reply.
Reading from PCM cells has scaled to nanoseconds, what is comparable with DRAM performance. Despite that you can directly overwrite cells without prior erasing them, writing is to be improved; and a pound to a penny, that’s what your team is doing now. Keep on advancing PCM!

Those will be more five years of TRIMing SSDs and block erasures.

(I meant that the link to your first post should have been http://www.micronblogs.com/2011/09/demonstrating-phase-change-memory-2/. Instead, the original link directs to RealSSD™ P400e.)

Comment on A Trillion Bits on a Fingertip by Mike Seibert

Mike Seibert — Tue, 13 Dec 2011 21:57:33 +0000

Actually, that is a single die in the photo. When we stack NAND die, they’re stacked vertically (not beside each other) and joined in a single black plastic package that then goes into the end product.

Each die has a x8 bus, but that doesn’t multiply when you stack several die in a package because the bus is still the same. So the package throughput for this part, regardless of the number of die, is 333 MB/s.

Comment on A Trillion Bits on a Fingertip by bbman

bbman — Sat, 10 Dec 2011 18:13:32 +0000

Heyyy, 20nm refers to dimensions of certian structures in the chip. Not the total chip size. It is a used to compare manufacturing technologies. Smaller means that means more bits are possible within a given chip size.