• “a significant milestone for the industry, one that’s likely to increase confidence in the technology.”
—Bob Merritt, analyst
InternetNews.com

• “proves wrong all those people who think that high-endurance devices will never be supported by advancing lithographies.”
—Jim Handy, analyst
Enterprise Storage Forum

• “Micron made a major announcement this week touting a new memory structure that simultaneously drives up the density and write performance of current Flash memory.”
IT Business Edge

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In fact, our 34nm process is so solid, we’ve even moved our super-high cycling Enterprise NAND parts to it. We just announced 34nm SLC and MLC Enterprise NAND parts that can hit 300,000 and 30,000 cycles, respectively. These new parts deliver unmatched density, cost-efficiency, and reliability and will open up new potential for NAND storage in enterprise applications.  Watch my quick explanation below to understand why.

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Multiple Routes to Quality & Reliability
More than any other segment, enterprise apps want high quality and high reliability NAND. While we create specially-designed “Enterprise NAND” that delivers super-low defect rates and high endurance for specific applications, there are other methods to increase endurance. For instance, some of our customers take advantage of the high density of our newest NAND to build systems with a surplus of capacity. Because there’s extra density, each cell is written less often, and the effective life of all the NAND goes up dramatically. Advanced wear-leveling algorithms will also provide advanced NAND with better endurance levels than it achieved in the past.

NAND Control Will See Breakthrough Innovation
Yes, developing NAND controller technology is more challenging with each process node, but it is also an area of heavy focus and technology investment. Micron, with SSD’s and other technologies in development, is ensuring that NAND is fit for the enterprise. Controllers will continue to improve along with the NAND changes—this is an area of tremendous innovation, and mirrors what occurred in HDD evolution.

Scaling—The Path Ahead
Some have suggested that only legacy process NAND is fit for enterprise applications. That’s simply not true. As noted above, there are multiple methods to achieve enterprise-class performance on advanced process NAND. And while we will continue to provide some legacy NAND for key applications, most enterprise customers will want to take advantage of the benefits new technology presents. In fact, this week we will introduce a new portfolio of ultra-reliable Enterprise NAND products designed on our mature 34nm NAND process – enabling the high density and better cost structure that only advanced process NAND can provide. Make sure to stay tuned to our blog for more on that later this week.

And we stated this summer at the Flash Memory Summit, NAND has plenty of room for further scaling improvements. Don’t let the naysayers fool you—the years ahead are going to be an exciting period of change and accelerating NAND adoption into hundreds of new applications. I’m looking forward to it.

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Simply put–what ultimately matters is having the lowest cost-per-bit solution in volume production at a given moment in time, not how many bits per cell are stored. Now, that said, there’s no question that being able to store more bits per cell results in lower cost.  However, there are some serious trade-offs that we think make this option not viable at this time.  Most notably–performance and reliability suffer.  In fact, we estimate that the performance (measured in write-cycle throughput) for going from two to three bits per cell using the same NAND architecture and process technology could be as much as halved. And reliability, (measured in write-cycle endurance) could be up to an order of magnitude worse (yes—up to 10x worse).  Scary stuff. Because having a product that may have a lower bit cost, but doesn’t meet today’s level of performance and reliability limits the value of that product.  It’s also worth noting the greater burden on the system implementation of going beyond today’s well-understood MLC technology, such as making sure the controller provides adequate ECC coverage.

Perhaps the most critical factor is the time frame of when the new product is introduced relative to the next-generation process technology.  So, for example–most NAND manufactures introduce MLC products first on their latest-and-greatest process node, and then introduce other products as the process matures.  But, if you introduce a new product with more than two bits per cell and your next-generation process technology is production-ready shortly thereafter, it is likely that your new product will not be successful, since the next generation process will provide lower cost, higher performance, and higher reliability with the good-old standard MLC.

Now, all that said, at our core we are innovators–and I’ll tell you that we are currently developing products that go beyond two bits per cell. But we also feel that the technology as a whole hasn’t come into its own just yet. It will, but what’s clear now is that lithographic scaling is the key to achieving the lowest costs while delivering the performance and reliability that the industry needs.

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We started working with Micron a little more than a year ago to leverage their work in NAND flash and look for ways to use those innovations to enable our own plans for our products. Ultimately it’s really a symbiotic relationship where each company can bring requirements, breakthroughs, goals, napkin sketches, all-the-above, to the table to understand the capabilities and (frankly) the wish lists for NAND in the storage space. Through that relationship, we learned about the work they were doing to extend the lifespan of NAND. This was right up our alley–because what they were proposing was a new NAND flash technology that was going to hit one million write cycles.  They dubbed it Enterprise NAND.

But, before we get to talking too much about Enterprise NAND, let’s talk a little about flash memory in general to provide context to how Violin is using the technology. You’re probably aware that standard flash–both SLC and MLC–has a limited lifetime. If not, here’s a quick overview: NAND has a given number of cycles (times) that it can be written to before it fails. Standard SLC NAND can be written to up to 100,000 times, which is great for certain applications like mobile phones, for example. Standard MLC NAND can be written to up to 10,000 times, and finds a good fit in devices like MP3 players. Ultimately, both of these variations of flash have ideal applications to call home. But there are still some applications that require longer write and erase cycles, such as with Tier Ø computing which is what Violin’s focused on.

As we looked to optimizations that we could make in our hardware, we identified four fundamental approaches to increase the lifespan of flash-based storage:
1.   Improve the efficiency of user writes for the flash media by reducing the write amplification;
2.   Improve wear leveling, which ensures individual “erase” blocks are used evenly throughout the system;
3.   Increase the capacity of the system, enabling the write load to be spread across more storage;
4.   Increase the endurance of the underlying flash devices.

At Violin, we’ve implemented the first three approaches into our system architecture. Micron’s Enterprise NAND brings the fourth element to the table. And together, we believe these techniques will dramatically improve the lifetime of flash-based systems, which need to endure the very strenuous write/erase cycles found in today’s data center operations.

We’re thrilled to see Micron extending the lifecycle of NAND and it’s been exciting to be able to work with Micron on such a cutting-edge approach. In fact, we believe extended-cycling NAND to be one of the most important flash memory innovations for enterprise and storage applications. It significantly accelerates the transition from performance disk drives to solid state storage. Stay tuned to see Violin products designed with Micron’s Enterprise NAND in 2009, ensuring a lifetime of reliable data for such applications such as content delivery, e-mail servers and enterprise file storage.

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In order to help folks better understand some of the claims out there, I thought I’d provide a quick overview on managing NAND on an SSD as well as some background on wear-leveling concepts.

First, understand that unlike DRAM and SRAM which can be read and written one word at a time, hard drives and SSDs are “block addressed” devices. The Logical Block on a hard drive or SSD is 512 bytes in size. On a hard drive, a given logical block is always on the same physical location region of the disk. On an SSD the relationship between physical and logical blocks is less direct due to endurance issues with NAND. If an operating system or program continuously addresses a limited number of logical blocks then those logical blocks will likely wear out before the rest of the NAND wears out.  That said, well-designed SSDs continually move logical blocks about the drive to minimize “hot spots” and reduce NAND wear.

Firmware running on the SSD controller takes care of these tasks in a process commonly referred to as wear-leveling.  Today all of the latest-generation SSDs implement complex wear-leveling schemes in an effort to efficiently utilize the available NAND cycles available.  Think of NAND memory on an SSD like a carpet in a house.  In a house with older carpet you will notice that the carpet becomes worn out in high-traffic areas but other areas like under furniture and the edges of the rooms the carpet is still new and unworn.  In this same house if the carpet was used evenly in all areas it would last much longer.  This is the same concept for an SSD—wear-leveling moves the high traffic areas evenly around the entire NAND array giving the SSD a much longer life.   Within the umbrella of wear-leveling there are a couple other concepts you will see in the industry—garbage collection and write amplification.

Garbage Collection

NAND has some constraints that are not ideal for use as a storage medium in a storage device like an SSD.  The storage area on a NAND device is broken into units called pages and blocks.  A page is typically 4KB in size and a block is a group of pages (64 to 128 pages to a block for today’s NAND devices).  In order to write data to a NAND device, it must be erased first.  The smallest unit that can be erased is a block. Once the block is erased the pages can be written one at a time until the block is filled.  It is undesirable to have to erase a block and move the data around on every single write that is received from the host because this process is slow—resulting in poor SSD performance.  The process is referred to as “read-modify-write”.  In order to avoid performing read-modify-write procedures, modern SSDs will keep a pool of blocks pre-erased and ready for new data.  When data is written to the same logical area repeatedly it is always written to a new physical area in the NAND. Along with the written data, a table that tells the controller where to locate the latest data is updated and the old locations are marked invalid.  At some point the drive runs out of pre-erased blocks and must re-claim the areas marked invalid by the firmware.  This process of reclaiming blocks is called garbage collection and SSDs must do it frequently or they will quickly run out of space.

To put this into an everyday example, imagine that you and your friends order two pizzas for dinner. The two pizzas arrive and soon everyone is busy moving slices of pizza onto their own plates. The only problem is there’s no room on the table for the requisite pitchers of beer. So you make the command decision to combine the remaining slices of pizza onto one pizza tray—creating new empty space on the table.  Your friends pour their beer and applaud your sheer brilliance…as a garbage collector!

Write Amplification

The amount of information written to the NAND is always greater than that written by the user because wear leveling and the garbage collection process generate some extra NAND writing.  Write amplification is a measure of the amount of data written to the NAND verses the amount of data written by the user to the SSD.    The objective of the firmware on the SSD is to be as efficient as possible to limit the extra NAND writes.

That said, there is a lot of misinformation about write amplification. All drives will have a worst case limit when the drive is nearly full. In this case, the write of a single 512byte logical block will result in at least one NAND page being written. With a page size of 4K the write amplification must, out of necessity, be 4kbytes/512bytes, for a write amplification of 8. However, most SSD vendors report something much closer to one, which would be the case for an empty drive and larger data transfer sizes.

So…next time you see new claims about SSD performance and endurance, keep these concepts in mind. They’re a good place to start judging whether they’re catching up or if you should be impressed.

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