Chris Smith: Eric, thanks for talking with me today. I’ve noticed that Micron has been focusing more and more energy on the mobile market. Today, the company introduced a new line of MCPs; could you tell me a bit about these products?

Eric Spanneut: We are announcing the adoption of our latest process technologies—both NAND and DRAM—to our line of high-end MCPs. It means that we have leveraged our 34nm single-level cell (SLC) technology on the NAND side, as well as our 50nm technology on the low-power DRAM side.

Chris: Is this the first 50nm designed into your MCP products?

Eric: This is our first monolithic 2Gb LPDRAM, which is being adopted by our MCP product line.

Chris: What range of the mobile market will these MCPs serve?

Eric: These products will serve the high-end feature phone market, and the smart phone market that uses open operating system like Windows Mobile, Android, or Symbian, as well as the nascent mobile internet device (MID) market.

Chris: I notice that this MCP uses LPDDR, but I know you manufacture LPDDR2; when will you transition this MCP to LPDDR2?

Eric: We see growing interest in LPDDR2, but first adoption by handset vendors won’t happen until second half of 2010. We expect LPDDR to be the front-runner in terms of volume for the next three to four years. That said, when the transition does begin, handset vendors will recognize significant advantages with LPDDR2, including reduced pin count, higher frequency and a better power budget.

Chris: So, if LPDDR2 has these benefits, why isn’t it being widely adopted at this time?

Eric: The mobile value chain is a very complex one with a complex ecosystem. It always takes a long time for a new technology to be massively adopted.

Chris: Back to today’s announcement; I imagine these die are much smaller than the packages that they go into. What are the benefits of using the latest process technology for these die inside the MCPs?

Eric: There are several benefits. The first one is that it allows us to be more competitive in the market place. The second benefit is that we are able to intercept smaller form factors by shrinking the dies. For example, we know that our 2Gb LPDDR can accommodate some small form factor designs that our competition’s LPDDR cannot accommodate. Finally, we want to minimize the number of dies we have in the package. It is better to have a 2Gb monolithic die in a package rather than two 1Gb monolithic die—not only because of cost, but also because of power and system optimization.

Chris: Will you provide different MCP densities?

Eric: Yes. We will start with 4Gb NAND and 2Gb LPDDR, and we’ll introduce higher densities-–up to 8Gb NAND and 8Gb LPDDR – as we see the handset market trend toward greater capacity requirements.

Chris: Do you have to increase package size by going to those higher densities?
Eric: The package size doesn’t change, just the package thickness as you stack more die.

Chris: Tell us about some of the trends you’re seeing in the mobile memory market and what’s driving these trends?

Eric: We see a polarization of the market place with a stronger high-end market and devices like smart phones booming. We also see more and more low-end phones being produced as well as a booming data card market which consumes lots of SLC NAND and low density low-power DRAM.

On the LPDDR side, the high-end market requires higher densities, higher performance and higher frequencies. Micron was actually the first to support 200 megahertz on LPDDR—it’s an important benchmark because certain chipsets require these higher frequencies to operate.    We’re also seeing some initial interest in LPDDR2, even though LPDDR will be the volume leader for several years.

On the NAND side, we see an increasing shift from NOR to NAND. There are a few reasons for this. Largely, the growing requirement for higher densities and multimedia technologies is driving this. Past a certain density, NAND presents a much better cost structure for these requirements. Chipset support is also shifting toward NAND–-the ecosystem is now set up to support the massive adoption of NAND.

There is also increased momentum for high-density embedded MMC (managed NAND) deployment. In the past, handset manufacturers preferred external mass storage to keep their BOM cost low and their architecture flexible. But now, handset vendors see embedded mass storage as a way to differentiate themselves in the high-end part of the market. Density really is a differentiator in the market today.

Embedded MMC should also get further traction with the 4.4 standard which will provide important booting and security features.

Chris: what is the NAND & NOR market breakdown?

Eric: In 2008, NOR still represented a majority of the non-volatile memory shipments in the handset space, while we expect it to only account for about one quarter of these in the 2012 time-frame.

Chris: What is Micron doing to provide extra value to handset manufacturers?

Eric: We work a lot with the entire mobile value chain. We work quite closely with operating system and chipset vendors. We spend a lot of time qualifying our memories with those key players. We also spend a lot of time developing additional software services, which improves the performance and endurance of our products.

All of this shows how much we’re committed to the mobile space and we believe our broader memory portfolio strongly positions us in the marketplace. We’re growing fast in the mobile market, we have had some major successes this year, and this new generation of MCPs really shows how competitive we are.

Chris: Eric, thanks again for your time, we look forward to talking with you again about innovations in the mobile market.

Eric: My pleasure.

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DDR3 SODIMM: Small package, big low-power performance

If you design electronics, you’re used to thinking of power savings and performance as opposite poles—you’ve typically had to trade one to get the other. But it really is possible to deliver low power with high performance. In fact, we’ve found ways to continually reduce DRAM power needs while still hitting aggressive performance targets. It’s a strategy we’re calling “performance efficiency.” We see lots of opportunity for our DRAM to make a significant difference in a variety of applications—now and in the years ahead. We can save power and still deliver unprecedented levels of performance.

As a proof point, today Micron announced a new line of high-performance DDR3 SODIMMs that run at just 1.35V (standard DDR3 DIMMs run at 1.5V). That .15V difference may seem miniscule, but it amounts to a significant power savings—our estimates put it at about 20%. But the cool thing is that these SODIMMs aren’t any slower than their power-hungry siblings. They can hit 1333 MT/s in stride—plenty of throughput for the latest generation of high-performance laptops. Check them out: view DDR3 1.35V SODIMMs.

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As data centers continue to multiply at unprecedented levels, the technology community has been looking for ways to make their products more energy efficient – because these are the products that use the power to keep the data centers humming.

A sneak peek inside one of these data centers would reveal thousands or tens of thousands of servers. Servers are similar to PCs in that they use the same microchips—CPUs and memory. Yes, memory, and lots of it. And as EE Times recently put it “the notoriously voracious microprocessor is passing the power-hog mantle to the DRAM,” consuming quite a surprising amount of power – approximately 15%, according to the Burton Group. And for every Watt of power that goes into a piece of IT equipment, it takes another Watt to power and cool it.

Bill Tschudi, program manager at Lawrence Berkley National Laboratory, said that the push to make data centers more energy efficient will include several items including improved IT practices and “advancements on the memory side.”

At Micron, we’ve taken a lead on these memory advancements with our own line of energy-efficient data center memory.

To illustrate how our memory is helping green up data centers, let’s compare standard DDR2 and DDR3 memory to our energy efficient line. Standard DDR2 and DDR3 used in data center servers typically operates at 1.8V and 1.5V, respectively. Through clever changes in the memory architecture, we were able to reduce the operating voltage on DDR2 to 1.5V and on DDR3 to 1.35V. This means that Micron’s 1.5V DDR2 can realize a whopping 58 percent power savings over the standard 1.8V memory modules while the 1.35V DDR3 uses 21 percent less power than its 1.5V predecessor. Over time, these energy efficiencies gained can add up to big cost savings while reducing the impact on Mother Earth; something we can all feel good about.

Our commitment to energy efficient memory doesn’t just stop at data centers. We’ve got some new innovations coming down the pike this week so stay tuned (or follow us using Twitter’s data center) to learn more on how Micron is leading the way in the energy efficient memory movement.

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