To put it in perspective, a terabit (128GB) is a HUGE amount of data—according to Tech Target, it’s more than enough to store all the contents of an entire library floor of academic journals (100GB)—reams of information all packed within a single NAND package.

But you’re probably not storing thousands of academic journals. For you and me it means more storage for downloaded movies, music, e-books, and photos. You probably don’t know how many NAND die are in your phone or SSD, but you do know how much it cost, which is what process improvements like these provide—more cost-effective, better storage solutions. Intel and Micron continue to lead the industry in moving innovative new NAND solutions to production.

Let me know what you think of our latest 20nm NAND by posting a comment below, or read more about our technology leadership on our Process Innovations page.

More exciting news from FMS: Yesterday Micron and Intel received the award for the Most Innovative Flash Memory Technology at the  Flash Memory Summit. The award recognizes our industry-leading 20nm NAND process technology.

Manufactured by our joint venture, IM Flash Technologies, the new device is a breakthrough in NAND process and design, providing approximately 50% more capacity than current technology And, for those who enjoy the gory details, the new 20nm 8GB device measures just 118mm2!

If you’re interested in reading more about our leading-edge NAND process technology, see our Innovations page.

Process shrinks require tinier, more-complex cells, which translates to lower performance and endurance. This has been true for generations of NAND process shrinks and is more or less a byproduct of the laws of physics. We’re approaching atomic dimensions (a single copper atom is .25nm), and it takes some extraordinary science to design circuits that can hold electrical charges at this scale.

With this new design however, we included some innovative new technology that will allow our 20nm NAND to eventually hit the same endurance and performance specifications as our current-generation NAND (25nm). We’re also continuing our pattern of keeping ECC (error correction code) requirements a generation lower than the competition. Our 20nm NAND will have similar ECC requirements to some competitors’ current NAND products, meaning they won’t require more ECC from the controller.

These are significant advancements that helps provide a viable path for NAND scaling and development. The end result is a great new product that’s going to enable even more innovation in mobile storage applications.

Chris Smith: Eric, thanks for talking with me today. I’ve noticed that Micron has been focusing more and more energy on the mobile market. Today, the company introduced a new line of MCPs; could you tell me a bit about these products?

Eric Spanneut: We are announcing the adoption of our latest process technologies—both NAND and DRAM—to our line of high-end MCPs. It means that we have leveraged our 34nm single-level cell (SLC) technology on the NAND side, as well as our 50nm technology on the low-power DRAM side.

Chris: Is this the first 50nm designed into your MCP products?

Eric: This is our first monolithic 2Gb LPDRAM, which is being adopted by our MCP product line.

Chris: What range of the mobile market will these MCPs serve?

Eric: These products will serve the high-end feature phone market, and the smart phone market that uses open operating system like Windows Mobile, Android, or Symbian, as well as the nascent mobile internet device (MID) market.

Chris: I notice that this MCP uses LPDDR, but I know you manufacture LPDDR2; when will you transition this MCP to LPDDR2?

Eric: We see growing interest in LPDDR2, but first adoption by handset vendors won’t happen until second half of 2010. We expect LPDDR to be the front-runner in terms of volume for the next three to four years. That said, when the transition does begin, handset vendors will recognize significant advantages with LPDDR2, including reduced pin count, higher frequency and a better power budget.

Chris: So, if LPDDR2 has these benefits, why isn’t it being widely adopted at this time?

Eric: The mobile value chain is a very complex one with a complex ecosystem. It always takes a long time for a new technology to be massively adopted.

Chris: Back to today’s announcement; I imagine these die are much smaller than the packages that they go into. What are the benefits of using the latest process technology for these die inside the MCPs?

Eric: There are several benefits. The first one is that it allows us to be more competitive in the market place. The second benefit is that we are able to intercept smaller form factors by shrinking the dies. For example, we know that our 2Gb LPDDR can accommodate some small form factor designs that our competition’s LPDDR cannot accommodate. Finally, we want to minimize the number of dies we have in the package. It is better to have a 2Gb monolithic die in a package rather than two 1Gb monolithic die—not only because of cost, but also because of power and system optimization.

Chris: Will you provide different MCP densities?

Eric: Yes. We will start with 4Gb NAND and 2Gb LPDDR, and we’ll introduce higher densities-–up to 8Gb NAND and 8Gb LPDDR – as we see the handset market trend toward greater capacity requirements.

Chris: Do you have to increase package size by going to those higher densities?
Eric: The package size doesn’t change, just the package thickness as you stack more die.

Chris: Tell us about some of the trends you’re seeing in the mobile memory market and what’s driving these trends?

Eric: We see a polarization of the market place with a stronger high-end market and devices like smart phones booming. We also see more and more low-end phones being produced as well as a booming data card market which consumes lots of SLC NAND and low density low-power DRAM.

On the LPDDR side, the high-end market requires higher densities, higher performance and higher frequencies. Micron was actually the first to support 200 megahertz on LPDDR—it’s an important benchmark because certain chipsets require these higher frequencies to operate.    We’re also seeing some initial interest in LPDDR2, even though LPDDR will be the volume leader for several years.

On the NAND side, we see an increasing shift from NOR to NAND. There are a few reasons for this. Largely, the growing requirement for higher densities and multimedia technologies is driving this. Past a certain density, NAND presents a much better cost structure for these requirements. Chipset support is also shifting toward NAND–-the ecosystem is now set up to support the massive adoption of NAND.

There is also increased momentum for high-density embedded MMC (managed NAND) deployment. In the past, handset manufacturers preferred external mass storage to keep their BOM cost low and their architecture flexible. But now, handset vendors see embedded mass storage as a way to differentiate themselves in the high-end part of the market. Density really is a differentiator in the market today.

Embedded MMC should also get further traction with the 4.4 standard which will provide important booting and security features.

Chris: what is the NAND & NOR market breakdown?

Eric: In 2008, NOR still represented a majority of the non-volatile memory shipments in the handset space, while we expect it to only account for about one quarter of these in the 2012 time-frame.

Chris: What is Micron doing to provide extra value to handset manufacturers?

Eric: We work a lot with the entire mobile value chain. We work quite closely with operating system and chipset vendors. We spend a lot of time qualifying our memories with those key players. We also spend a lot of time developing additional software services, which improves the performance and endurance of our products.

All of this shows how much we’re committed to the mobile space and we believe our broader memory portfolio strongly positions us in the marketplace. We’re growing fast in the mobile market, we have had some major successes this year, and this new generation of MCPs really shows how competitive we are.

Chris: Eric, thanks again for your time, we look forward to talking with you again about innovations in the mobile market.

Eric: My pleasure.

• “a significant milestone for the industry, one that’s likely to increase confidence in the technology.”
—Bob Merritt, analyst
InternetNews.com

• “proves wrong all those people who think that high-endurance devices will never be supported by advancing lithographies.”
—Jim Handy, analyst
Enterprise Storage Forum

• “Micron made a major announcement this week touting a new memory structure that simultaneously drives up the density and write performance of current Flash memory.”
IT Business Edge

In fact, our 34nm process is so solid, we’ve even moved our super-high cycling Enterprise NAND parts to it. We just announced 34nm SLC and MLC Enterprise NAND parts that can hit 300,000 and 30,000 cycles, respectively. These new parts deliver unmatched density, cost-efficiency, and reliability and will open up new potential for NAND storage in enterprise applications.  Watch my quick explanation below to understand why.

Multiple Routes to Quality & Reliability
More than any other segment, enterprise apps want high quality and high reliability NAND. While we create specially-designed “Enterprise NAND” that delivers super-low defect rates and high endurance for specific applications, there are other methods to increase endurance. For instance, some of our customers take advantage of the high density of our newest NAND to build systems with a surplus of capacity. Because there’s extra density, each cell is written less often, and the effective life of all the NAND goes up dramatically. Advanced wear-leveling algorithms will also provide advanced NAND with better endurance levels than it achieved in the past.

NAND Control Will See Breakthrough Innovation
Yes, developing NAND controller technology is more challenging with each process node, but it is also an area of heavy focus and technology investment. Micron, with SSD’s and other technologies in development, is ensuring that NAND is fit for the enterprise. Controllers will continue to improve along with the NAND changes—this is an area of tremendous innovation, and mirrors what occurred in HDD evolution.

Scaling—The Path Ahead
Some have suggested that only legacy process NAND is fit for enterprise applications. That’s simply not true. As noted above, there are multiple methods to achieve enterprise-class performance on advanced process NAND. And while we will continue to provide some legacy NAND for key applications, most enterprise customers will want to take advantage of the benefits new technology presents. In fact, this week we will introduce a new portfolio of ultra-reliable Enterprise NAND products designed on our mature 34nm NAND process – enabling the high density and better cost structure that only advanced process NAND can provide. Make sure to stay tuned to our blog for more on that later this week.

And we stated this summer at the Flash Memory Summit, NAND has plenty of room for further scaling improvements. Don’t let the naysayers fool you—the years ahead are going to be an exciting period of change and accelerating NAND adoption into hundreds of new applications. I’m looking forward to it.

The test pits our single- and dual-plane SLC devices and NANDCode™ FTL software against Samsung’s OneNAND™ running on Microsoft’s FTL. The test system is a TI OMAP™ 3430 development platform running Windows Mobile® 6.5 OS. We changed out the onboard NAND with a simple PISMO card swap and then ran a 10MB system performance test.

The results are impressive and undeniable. The key is our custom NANDCode FTL software, which enables advanced performance features like dual-plane programming.

Watch the video below to see why some of our competitors’ customers have been willing to open their design cycles to take advantage of the big NAND performance gains offered by Micron’s MCPs.

Visit our Web site to learn more about our NANDCode software and how you can use it to boost performance in your next mobile design.