abby  on October 18th, 2009

What’s the point of the tiny NAND? Who really cares? And the video demonstration was pointless…

Kevin  on October 19th, 2009

Sorry if the story and video were not useful to you. This information is targeted to people who are familiar with semiconductor design and flash memory technology – specifically for large enterprise organizations. But, from a consumer standpoint, you probably have flash memory in your handheld electronics, such as a digital camera, MP3 player, cell phone. In these products, tiny flash memory provides more storage capacity at a lower cost.

The video explains the increased cycle rates of our enterprise NAND, which increases overall reliability – a key requirement for enterprise applications. As flash memory replaces hard drives in enterprise applications, the end user will realize faster Internet searches and downloads, and flash memory consumes less power than hard drives, so in many ways it contributes to a greener earth.

Thanks,
Kevin

sf  on October 19th, 2009

I didn’t know that MLC endurance had dropped to 1.5k cycles at the 50nm node. When people in the consumer space talk about MLC and SLC differences they use a 10x difference (so 10k cycles). For today’s mp3 / digital photo applications is 1.5k or 5k the expected endurance? What about consumer SSDs? Can you share anything on why endurance is increasing despite going to a smaller process node?

Kevin  on October 19th, 2009

SF,
Great questions. I think you may have misread the chart somewhat. The 1.5k cycle parts were some of the first generation 34nm parts we produced, not 50nm. NAND will always have lower endurance rates on a brand new process; as the design is refined and perfected, rates will go up—that’s what I was trying to show with the timeline.

The NAND parts in your USB drive or SD card may have endurance rates below 1k, because cost is the primary driver for those applications. Endurance really isn’t an issue unless you expect your thumb drive to last more than five years and are frequently filling it up. MP3 players and photo cards may have slightly higher rates—depending on the manufacturer and the NAND they source. Consumer SSDs are an entirely different story. They write and rewrite data regularly, and need higher endurance rates. That’s why I’m so excited about our new MLC Enterprise NAND. At 30k cycles, it has enough endurance for consumer SSDs, allowing cost-effective MLC to reach the SSD market.

As to your last question, we’ve been able to increase endurance on the 34nm node through the months of experience and process tuning we’ve had since beginning production on 34nm nearly a year ago. It’s one of the advantages of being the first to develop on new process nodes. Because of this refinement, we’ve been able to move nearly our entire NAND product line to 34nm.

ck  on October 19th, 2009

Regarding the Enterprise NAND, there is no free lunch, I guess. Is there any trade-off by exchanging higher endurance? like the timing setting has to be slower to make the Flash cell life longer? Will that impact the speed of the flash comparing with normal 34nm MLC/SLC?

hehe  on October 19th, 2009

Hey, Kevin:

Several questions here:

1. The 30,000 cycle MLC only applies to 3bit MLC right? If you used the technology to boost the 2bit MLC stuff, shouldn’t you expect 60,000 cycles out of 2bit MLC, which the X25-M uses currently?

2. Can you give an estimate of when we will see 34nm SLC in next generation X25-E? Q4, 2009 or Q1, 2010? I hope it is the 300K cycle SLC being used for the next gen x25-e?

3. Did Micron sacrifice write latency for the write cycle? 3bit MLC inherently would have slower access latency. Can you quantify the access latency of your 3bit MLC technology? And would Intel introduce another version of X25-M soon to use the 3bit stuff?

Thanks

Kevin  on October 20th, 2009

CK, you’re correct that there are some tradeoffs in programming and erase times in order to achieve the increased endurance. However, this reduction in write latency is moderate, and in typical enterprise applications with lots of parallelism (many NAND channels and devices per channel), it is pretty much negligible–well worth the tremendous increase in cycling. (If you would like a data sheet to better quantify this, please view them at micron.com and request access. Note you will need a valid business email address)

Kevin

Kevin  on October 20th, 2009

Questions? No problem.

1. 30,000 cycles is for our 2-bit MLC technology. Note our standard endurance specification is 5,000 cycles for 2-bit MLC, so this is a 6X increase. We are working on some cool technology to increase endurance for 3-bit MLC as well, but nothing to report today.

2 & 3. Re: the x25-M/E, I can’t comment on Intel’s product plans. Re: Latency, please see my response to CK’s question.

Kevin