The Scoop on 25nm TLC NAND
We put Kevin Kilbuck, our director of strategic NAND marketing, in front of a whiteboard so we could get some high-level perspective on today’s Micron/Intel 25nm Triple Level Cell (TLC) NAND technology announcement. Is this brief video he reviews MLC, SLC, and TLC technology and demonstrates what a 25nm TLC NAND offers for consumer storage.
Watch to learn more.
4 Comments to “The Scoop on 25nm TLC NAND”
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Hi,
I’m wondering if you can share a few more general details of your new 25nm TLC.
I’m interrested in page size, ballpark figures for number of program cycles, internal and external transfer rates (sequential R/W), and latency/IOPS for small block random R/W.
I’m also interrested in some info on the type of USB flash drives you put TLC in. Are you pushing the adoption of USB 3.0? With the type of read bandwidth i suspect you get out of these dies, it would make sense.
Is there any chance we may see some speedy netbook boot drives with TLC in 2011?
GulLLars
That sounds really great capacity wise but I am a little confused as you said the performance is dropping. Are there any performance tests by now, about read and write speed ? And it would be very interesting to know how the TLC compares to the MLC and SLC in the point of power consumption.
Regards Jan
There is already a pretty big performance differences seen between SLC and MLC technology. How does TLC measure up in terms of performance? How does it fare to SLC or MLC? What kind of initiatives is Micron pursuing to allow for faster random write access?
Thanks for all your comments.
GulLLars, unfortunately, for competitive reasons I can’t publicly share any specific performance data about our TLC products right now.
Today, USB drives follow the 1.0/2.0 specs. We are not 100% sure when USB 3.0 products will appear in the market, as this depends more on the host support. You are correct that USB 3.0 is significantly faster than 2.0, and there is the real possibility of USB drives requiring faster NAND products for a portion of the market that may place value on faster data transfers between the host and drive. As such, Micron supports the ONFI 2.2 synchronous interface, reaching speeds of up to 200 MT/sec, on all of our high-capacity 25nm NAND products, including the TLC version discussed in my video.
I also can’t speak publicly about Micron’s SSD plans, but suffice it to say that in general we expect TLC-based SSDs to emerge in the market over the next few years.
Jan/Stevo, yes, TLC NAND has some inherent performance disadvantages against MLC (and SLC) designs due to its basic structure. Storing more bits per cell makes it more difficult to accurately read or write the cell, which means that the NAND has to verify the cell data multiple times for every read (and sometimes re-write and re-verify). This slows performance and increases wear rates.
Comparing a single-die for a given process technology, TLC power on write cycles is slightly higher than MLC (and MLC is slightly higher than SLC) for the reasons stated above. However, you must also consider the density. In many applications, the NAND density is increasing over time (for example, from 4GB to 8GB). Because we are also increasing the NAND density, the power required to write a given amount of data (for example 64MB) actually goes down. This can be a major benefit in applications, such as SSDs, then tend to write fixed data sizes.
Achieving faster random write performance is as much a function of the NAND product as it is the system architecture. Yes, as NAND continues to scale and/or we add more bits per cell, NAND gets inherently slower, most notably for random writes (array programming time). On the NAND side, what we are doing to fix this is by introducing new protocols that allow systems to take advantage of the parallelism of NAND. The first step in this process will be via products that adhere to the recently-announced ONFI EZ-NAND protocol. On the system side, one of most commonly used techniques is to use DRAM or SRAM as a buffer and effectively “hide” NAND latencies.
-Kevin